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May 1997
NDH8503N Dual N-Channel Enhancement Mode Field Effect Transistor
General Description
SuperSOT -8 N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.
TM
Features
3.8 A, 30 V. RDS(ON) = 0.033 @ VGS = 10 V RDS(ON) = 0.05 @ VGS = 4.5 V. Proprietary SuperSOTTM-8 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability.
____________________________________________________________________________________________
5 6 7 8
4 3 2 1
Absolute Maximum Ratings T A = 25C unless otherwise note
Symbol VDSS VGSS ID PD TJ,TSTG RJA RJC Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Maximum Power Dissipation Operating and Storage Temperature Range
(Note 1 ) (Note 1)
NDH8503N 30 20 3.8 10.5 0.8 -55 to 150
Units V V A
W C
THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1) (Note 1)
156 40
C/W C/W
(c) 1997 Fairchild Semiconductor Corporation
NDH8503N Rev.C
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 A VDS = 24 V, VGS = 0 V TJ = 55oC Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V VDS = VGS, ID = 250 A TJ = 125oC Static Drain-Source On-Resistance VGS = 10 V, ID = 3.8 A TJ = 125oC VGS = 4.5 V, ID = 3.2 A ID(on) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd On-State Drain Current VGS = 10 V, VDS = 5 V VGS = 4.5 V, VDS = 5 V Forward Transconductance VDS = 5 V, ID = 3.8 A VDS = 15 V, VGS = 0 V, f = 1.0 MHz DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance 500 310 125 pF pF pF 10.5 9 9 S 1 0.8 1.67 1.04 0.027 0.04 0.041 30 1 10 100 -100 V A A nA nA
ON CHARACTERISTICS (Note 2) Gate Threshold Voltage 2 1.6 0.033 0.06 0.05 A V
SWITCHING CHARACTERISTICS (Note 2) Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 10 V, ID = 3.8 A, VGS = 4.5 V VDD = 10 V, ID = 1 A, VGS = 10 V, RGEN = 6 10 15 20 9 18 1.8 4.2 18 28 35 18 25 ns ns ns ns nC nC nC
NDH8503N Rev.C
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max 0.67
(Note 2)
Units A V
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VSD
otes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design.
Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.67 A 0.72
1.2
PD(t) =
R JA(t)
T J -TA
=
T J -TA R JC+RCA(t)
= I 2 (t) x RDS(ON ) D
TJ
Typical RJA for single device operation using the board layout shown below on 4.5"x5" FR-4 PCB in a still air environment: 156oC/W when mounted on a 0.0025 in2 pad of 2oz copper.
Scale 1 : 1 on letter size paper. 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDH8503N Rev.C
Typical Electrical Characteristics
20 2.5
V GS =10V
I D , DRAIN-SOURCE CURRENT (A) 16
6.0 5.0
4.5 4.0
R DS(on) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE
VGS = 3.5V
2.25 2 1.75 1.5 1.25 1 0.75
4.0 4.5 5.0 6.0 7.0 10
12
3.5
8
4
3.0
0 0 0.5 V
DS
1 1.5 2 , DRAIN-SOURCE VOLTAGE (V)
2.5
3
0
4
8 12 I D , DRAIN CURRENT (A)
16
20
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Gate Voltage and Drain Current.
1 .8
2
I D = 3.8A
DRAIN-SOURCE ON-RESISTANCE
DRAIN-SOURCE ON-RESISTANCE 1 .6
V
1.75
GS
= 10V TJ = 125C
V GS = 10V
R DS(on), NORMALIZED
R DS(ON) , NORMALIZED
1 .4
1.5 1.25
1 .2
25C
1 0.75
1
0 .8
-55C
0.5 0.25 0 4 I
D
0 .6 -50
-25
0
J
25
50
75
100
125
150
T , JUNCTION TEMPERATURE (C)
8 12 , DRAIN CURRENT (A)
16
20
Figure 3. On-Resistance Variation with Temperature.
Figure 4. On-Resistance Variation with Drain Current and Temperature.
20
1.2
25C
16 I , DRAIN CURRENT (A)
GATE-SOURCE THRESHOLD VOLTAGE
V DS = 5V
T = -55C J
VDS = VGS
1.1
I D = 250A
125C
V th, NORMALIZED
1
12
0.9
8
0.8
D
4
0.7
0 1 1.5 V
GS
2 2.5 3 3.5 , GATE TO SOURCE VOLTAGE (V)
4
4.5
0.6 -50
-25
0 25 50 75 100 T , JUNCTION TEMPERATURE (C)
J
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with Temperature.
NDH8503N Rev.C
Typical Electrical Characteristics
1.12 DRAIN-SOURCE BREAKDOWN VOLTAGE 15
I
1.08
D
= 250A
I , REVERSE DRAIN CURRENT (A)
5 1
VGS =0V TJ = 125C 25C -55C
BV DSS , NORMALIZED
1.04
0 .1
1
0 .0 1
0.96
0 .0 0 1
0.92 -50
S
-25
0 T
J
25 50 75 100 , JUNCTION TEMPERATURE (C)
125
150
0 .0 0 0 1 0 0 .2 V
SD
0 .4 0.6 0 .8 1 , BODY DIODE FORWARD VOLTAGE (V)
1 .2
Figure 7. Breakdown Voltage Variation with Temperature.
Figure 8. Body Diode Forward Voltage Variation with Current and Temperature.
1500 1000 800 CAPACITANCE (pF) 500 300 200
10
I D = 3.8A
V GS, GATE-SOURCE VOLTAGE (V) 8
VDS = 10V
15V 20V
Ciss Coss
6
4
Crss
100
f = 1 MHz V GS = 0 V
2
50 0 .1
0 .2 V
0 .5
DS
1
3
5
10
30
0 0 5 10 Q g , GATE CHARGE (nC) 15 20
, DRAIN TO SOURCE VOLTAGE (V)
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
VDD
t d(on)
t on tr
90%
t off t d(off)
90%
tf
V IN
D
RL V OUT
DUT
VGS
VOUT
R GEN
10%
10%
INVERTED
G
90% S
V IN
10%
50%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
NDH8503N Rev.C
Typical Electrical and Thermal Characteristics
20 20
V DS = 5V
, TRANSCONDUCTANCE (SIEMENS) 16
TJ = -55C
I , DRAIN CURRENT (A)
10 5
S RD (O
N)
LIM
IT
10 0u s 1m s
10 ms s
25C
12
125C
1
10
0m
0.3 0.1
1s
8
V R
GS
= 10V
SINGLE PULSE
J A
10 s DC
4
D
= See Note 1 = 25C
g
FS
0.03 0 0 4 I
D
TA
8
12
16
20
0.01 0.1
0.2
, DRAIN CURRENT (A)
0.5 1 2 5 10 V , DRAIN-SOURCE VOLTAGE (V)
DS
30
50
Figure 13. Transconductance Variation with Drain Current and Temperature.
Figure 14. Maximum Safe Operating Area.
1
TRANSIENT THERMAL RESISTANCE
D = 0.5 0.2
r(t), NORMALIZED EFFECTIVE
R
0.1
0.1 0.05
JA (t) = r(t) * R JA R JA = See Note 1
P(pk)
0.02 0.01
t1
Single Pulse
0.01
t2
TJ - T
=P *R (t) JA Duty Cycle, D = t1 / t 2
A
0.001 0.0001
0.001
0.01
0.1 t 1 , TIME (sec)
1
10
100
300
Figure 15. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1. Transient thermal response will change depending on the circuit board design.
NDH8503N Rev.C

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